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10-18
D(P).DDRD
Control Data
(1) In multiple CPU system, data stored in a device specified by another CPU (n) ( ) or later is
stored by the number of read points specified by ( +1) into a device specified by host CPU
( ) or later.
(2) Whether to complete the D(P).DDRD instruction normally can be checked by the completion
device ( +0) and completion status display device ( +1).
(a) END processing in scan data that CPU completed the instruction turns on the device
and the next END processing turns off the device.
(b) This device turns on/off depending on the status upon completion of the instruction.
• Normal completion: Off
• Error completion: Turns on at END processing in the scan where the instruction has
been completed, and turns off at the next END processing (At error completion, an
error code is stored at control data ( +0): Completion status)).
(3) The number of blocks used for the instruction depends on the number of read points (refer to
Section 12.1).
Number of blocks used for the instruction
(4) The instruction will be completed abnormally when there are no empty blocks in the multiple
CPU high speed transmission area.
Set the number of blocks used for the instruction at special registers (SD796 to SD799), and
use the special relays (SM796 to SM799)as an interlock prevent error completion (refer to
Section 12.1).
Device Item Setting data Setting range Set by
+0
Completion status
An execution result upon completion of the
instruction is stored.
0000(H): No errors (normal completion)
Other than 0000(H): Error code (error completion)
–– System
+1
Number of read
points
Set the number of read points in units of words. 1 to 100 User
Number of read points
specified by the instruction
D(P).DDRD instruction
1 to 100 1
S1
S1
D1
S1
S2
Start device number of the
storage location for read data
D2
Number of read points
S1 +1
Host CPU
(CPU that requests reading)
Another CPU n
(CPU to be read)
Strat device number of the storage
location where read has been stored
S1
D2 D2
S1