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10-6
(6) The multiple CPU high-speed transmission dedicated instructions that can be executed
concurrently
For the Universal model QCPU, the multiple CPU high-speed transmission dedicated
instructions can be concurrently executed within the range satisfying the following formula.
When the number of blocks used for the multiple CPU high-speed transmission dedicated
instructions exceeds the total number of blocks in the multiple CPU high speed transmission
area, the instruction will not be executed in the scan (no processing) but executed at the
next scan.
Note that the instruction will be completed abnormally when the number of empty blocks in
the multiple CPU high speed transmission area is less than the setting values of SD796 to
SD799 (maximum number of used blocks for multiple CPU high-speed transmission
dedicated instruction setting) at the execution of the instruction.
The following table shows execution possibility of the multiple CPU high-speed transmission
dedicated instructions when the number of empty blocks in the multiple CPU high speed
transmission area is less than the number of blocks used for the multiple CPU high-speed
transmission dedicated instructions or the setting values of SD796 to SD799.
The number of blocks that
can be used in each CPU
Total number of blocks used for the
instructions concurrently executed
Magnitude relation between the number of blocks
used for the instructions*1 and
the number of empty
blocks
Magnitude relation
between SD setting value
and the number of empty blocks
SD setting value*
3
Number of empty blocks*
2
SD setting value*
3
Number of empty blocks*
2
Number of blocks used
for the instruction*1
Number of empty blocks*2
Number of blocks used
for the instruction*1
Number of empty blocks*2
Executed Not executed (no processing)
Completed abnormally
*1:The number of blocks used for the multiple CPU high-speed transmission dedicated instruction.
*2:The number of empty blocks in the multiple CPU high-speed transmission area.
*3:Setting values from SD796 of SD799.